REV. 1.1.3 LOW VOLTAGE DUART WITH 16-BYTE FIFO PIN DESCRIPTIONS Pin Description NAME" />
參數(shù)資料
型號： XR16L2550IM-F
廠商： Exar Corporation
文件頁數(shù)： 23/44頁
文件大?。?/td> 0K
描述： IC UART FIFO 16B DUAL 48TQFP
標準包裝： 250
特點： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
規(guī)程： RS232
電源電壓： 2.25 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 1016-1278
XR16L2550
3
REV. 1.1.3
LOW VOLTAGE DUART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME
32-QFN
PIN #
44-PLCC
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
18
19
20
29
30
31
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A/B during a data bus transac-
tion.
D7
D6
D5
D4
D3
D2
D1
D0
2
1
32
31
30
29
28
27
9
8
7
6
5
4
3
2
3
2
1
48
47
46
45
44
IO
Data bus lines [7:0] (bidirectional).
IOR#
14
24
19
I
Input/Output Read Strobe (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an internal
register pointed to by the address lines [A2:A0]. The data byte is
placed on the data bus to allow the host processor to read it on
the rising edge.
IOW#
12
20
15
I
Input/Output Write Strobe (active low). The falling edge instigates
an internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address
lines.
CSA#
7
16
10
I
UART channel A select (active low) to enable UART channel A in
the device for data bus operation.
CSB#
8
17
11
I
UART channel B select (active low) to enable UART channel B in
the device for data bus operation.
INTA
22
33
30
O
UART channel A Interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTA is set
to the active mode (active high) and OP2A# output to a logic 0
when MCR[3] is set to a logic 1. INTA is set to the three state
mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0
(Default).
INTB
21
32
29
O
UART channel B Interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTB is set
to the active mode and OP2B# output to a logic 0 when MCR[3] is
set to a logic 1. INTB is set to the three state mode and OP2B# to
a logic 1 when MCR[3] is set to a logic 0 (Default).
TXRDYA#
-
1
43
O
UART channel A Transmitter Ready (active low). The output
provides the TX FIFO/THR status for transmit channel A. If
it is not used, leave it unconnected.
RXRDYA#
-
34
31
O
UART channel A Receiver Ready (active low). This output pro-
vides the RX FIFO/RHR status for receive channel A. If it is not
used, leave it unconnected.
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