XR16L2551
9
REV. 1.1.3
LOW VOLTAGE DUART WITH POWERSAVE
2.3
Device Reset
The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to
their default state (see Table 14). An active high pulse of at least 40 ns duration will be required to activate the
reset function in the device.
2.4
Device Identification and Revision
The L2551 provides a Device Identification code and a Device Revision code to distinguish the part from other
devices and revisions. To read the identification code from the part, it is required to set the baud rate generator
registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x02 to indicate L2551
and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means
revision A.
2.5
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,
but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the L2551 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in
Channel A and B Internal Registers
Each UART channel in the L2551 has a standard register set for controlling, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratch pad register (SPR).
2.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE
CSA#
CSB#
FUNCTION
1
UART de-selected
0
1
Channel A selected
1
0
Channel B selected
0
Channel A and B selected
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE
CS#
A3
FUNCTION
1
N/A
UART de-selected
0
Channel A selected
0
1
Channel B selected