參數(shù)資料
型號: XR16L2751CMTR-F
廠商: Exar Corporation
文件頁數(shù): 1/50頁
文件大?。?/td> 0K
描述: IC UART FIFO 64B DUAL 48TQFP
標(biāo)準(zhǔn)包裝: 1,500
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.25 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
APRIL 2010
REV. 1.2.3
GENERAL DESCRIPTION
The XR16L27511 (2751) is a low voltage dual
universal asynchronous receiver and transmitter
(UART) with 5 Volt tolerant inputs. The device
includes
2
additional
capabilities
over
the
XR16L2750: Intel and Motorola data bus selection
and a “PowerSave” mode to further reduce sleep
current to a minimum during sleep mode. The 2751’s
register set is compatible to the ST16C2550 and
XR16C2850 but with added functions. It supports the
Exar’s enhanced features of 64 bytes of TX and RX
FIFOs, programmable FIFO trigger level, FIFO level
counters, automatic hardware and software flow
control, automatic RS-485 half duplex direction
control, and a complete modem interface. Onboard
registers provide the user with operational status and
data error tags. An internal loopback capability allows
onboard diagnostics. Independent programmable
baud rate generator is provided in each UART
channel to support data rates up to 6.25 Mbps.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787
APPLICATIONS
Portable and Battery Operated Appliances
Wireless Access Servers
Ethernet Network Routers
Cellular Data Devices
Telecommunication Network Routers
Factory Automation and Process Controls
FEATURES
2.25 to 5.5 Volt Operation
5 Volt Tolerant Inputs
Functionally Compatible to ST16C2550 and
XR16C2850 with 4 additional inputs
Intel or Motorola Data Bus Interface Select
Two Independent UARTs
Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt,
and 3 Mbps at 2.5 Volt with 8X sampling rate
64 bytes of Transmit and Receive FIFOs
Transmit and Receive FIFO Level Counters
Programmable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Selectable RTS Flow Control Hysteresis.
Automatic Software (Xoff/Xon) Flow Control
Automatic RS-485 2-wire Half-duplex Direction
Control to the Transceiver via RTS#
Full Modem Interface
Infrared
Receive and Transmit Encoder/
decoder
PowerSave Feature reduces sleep current to 15
A at 3.3 Volt
Device Identification
Crystal or external clock input
Industrial and Commercial Temperature ranges
48 TQFP Package (7 x 7 x 1.0 mm)
FIGURE 1. XR16L2751 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
Intel or
Motorola
Data Bus
Interface
UART Channel A
64 Byte TX FIFO
64 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
2.25 to 5.5 Volt VCC
GND
*5 Volt Tolerant Inputs
(Except XTAL1)
2751BLK
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA# (CS#)
16/68#
CSB# (A3)
INTA (IRQ#)
INTB (logic 0)
PwrSave
IOW# (R/W#)
IOR# (VCC)
Reset (Reset#)
CLKSEL
HDCNTL#
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
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