參數(shù)資料
型號(hào): XR16L2552IJ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
中文描述: 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 37/47頁
文件大小: 748K
代理商: XR16L2552IJ
xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
37
AC ELECTRICAL CHARACTERISTICS
Unless Otherwise Noted: TA=-40
o
to +85
o
C, Vcc is 2.25V to 5.5V,
70 pF load where applicable
S
YMBOL
P
ARAMETER
L
IMITS
2.5
M
IN
M
AX
L
IMITS
3.3
M
IN
M
AX
L
IMITS
5.0
M
IN
M
AX
U
NIT
-
Crystal Frequency
16
20
24
MHz
CLK
External Clock Low/High Time
31
17
10
ns
OSC
External Clock Frequency
16
30
50
MHz
T
AS
Address Setup Time
10
10
10
ns
T
AH
Address Hold Time
10
10
10
ns
T
CS
Chip Select Width
150
75
50
ns
T
RD
IOR# Strobe Width
150
75
50
ns
T
DY
Read Cycle Delay
150
75
50
ns
T
RDV
Data Access Time
125
70
45
ns
T
DD
Data Disable Time
0
45
0
30
0
30
ns
T
WR
IOW# Strobe Width
150
75
50
ns
T
DY
Write Cycle Delay
150
75
50
ns
T
DS
Data Setup Time
25
20
15
ns
T
DH
Data Hold Time
15
10
10
ns
T
WDO
Delay From IOW# To Output
150
75
50
ns
T
MOD
Delay To Set Interrupt From MODEM Input
150
75
50
ns
T
RSI
Delay To Reset Interrupt From IOR#
150
75
50
ns
T
SSI
Delay From Stop To Set Interrupt
1
1
1
Bclk
T
RRI
Delay From IOR# To Reset Interrupt
150
75
50
ns
T
SI
Delay From Stop To Interrupt
150
75
50
ns
T
INT
Delay From Initial INT Reset To Transmit
Start
8
24
8
24
8
24
Bclk
T
WRI
Delay From IOW# To Reset Interrupt
150
75
50
ns
T
SSR
Delay From Stop To Set RXRDY#
1
1
1
Bclk
T
RR
Delay From IOR# To Reset RXRDY#
150
75
50
ns
T
WT
Delay From IOW# To Set TXRDY#
150
75
50
ns
T
SRT
Delay From Center of Start To Reset TXRDY#
8
8
8
Bclk
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