參數(shù)資料
型號: XR16L2552IJ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
中文描述: 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 5/47頁
文件大小: 748K
代理商: XR16L2552IJ
xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
5
RIB#
27
31
I
UART channel B Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
MFA#
32
35
O
Multi-Function Output Channel A. This output pin can function as the OP2A#,
BAUDOUTA#, or RXRDYA# pin. One of these output signal functions can be
selected by the user programmable bits 1-2 of the Alternate Function Register
(AFR). These signal functions are described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is a logic 0
when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a
logic 1 condition after a reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate
clock output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data
transfers. If using the 48-TQFP package, this output is already available at pin
31.
If it is not used, leave it unconnected.
MFB#
14
19
O
Multi-Function Output ChannelB. This output pin can function as the OP2B#,
BAUDOUTB#, or RXRDYB# pin. One of these output signal functions can be
selected by the user programmable bits 1-2 of the Alternate Function Register
(AFR). These signal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is a logic 0
when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a
logic 1 condition after a reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate
clock output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data
transfers. If using the 48-TQFP package, this output is already available at pin
8.
If it is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1
5
11
I
Crystal or external clock input.
XTAL2
7
13
O
Crystal or buffered clock output.
RESET
16
21
I
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will reset the
internal registers and all outputs. The UART transmitter output will be held at
logic 1, the receiver input will be ignored and outputs are reset during reset
period (see External Reset Conditions).
VCC
29, 42
44, 33
Pwr
2.25V to 5.5V power supply. All input pins are 5V tolerant.
GND
6, 17
22, 12
Pwr
Power supply common, ground.
Pin Description
N
AME
48-TQFP
P
IN
#
44-PLCC
P
IN
#
T
YPE
D
ESCRIPTION
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