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參數(shù)資料
| 型號： | XR16L2552IM-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 44/45頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B DUAL 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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XR16L2552
8
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.2
2.5
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select
the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure,
send transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown
in Table 1.
2.6
Channel A and B Internal Registers
Each UART channel in the L2552 has a set of enhanced registers for controlling, monitoring and data loading
and unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and a user accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabilities, the L2552 offers enhanced feature registers (AFR,
EFR, Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control, automatic Xon/Xoff
software flow control, and simultaneous writes to both channels. All the register functions are discussed in full
detail later in “UART INTERNAL REGISTERS” .
2.7
Simultaneous Write to Channel A and B
During a write mode cycle, the setting of Alternate Function Register (AFR) bit-0 to a logic 1 will override the
CHSEL selection and allows a simultaneous write to both UART channel sections. This functional capability
allow the registers in both UART channels to be modified concurrently, saving individual channel initialization
time. Caution should be exercised, however, when using this capability. Any in-process serial data transfer
may be disrupted by changing an active channel’s mode.
2.8
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B (MF# A/B becomes RXRDY# A/B output when AFR[2:1] = ‘10’) and TXRDY# A/B output
pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode
operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for
more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1).
When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the L2552 is
placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-
3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block
sequence determined by the programmed trigger level. The following table show their behavior. Also see
Figure 18 through Figure 23.
TABLE 1: CHANNEL A AND B SELECT
CS#
CHSEL
FUNCTION
1
X
UART de-selected
0
1
Channel A selected
0
Channel B selected
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16L2552IMTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 16Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L2552IMTR-F |
| XR16L2750 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2750_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2750CJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2750CJ-0A-EB | 功能描述:UART 接口集成電路 Supports L2750 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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