參數(shù)資料
型號: XR16L2550IL-F
廠商: Exar Corporation
文件頁數(shù): 1/44頁
文件大小: 0K
描述: IC UART FIFO 16B DUAL 32QFN
標準包裝: 490
特點: *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: RS232
電源電壓: 2.25 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
SEPTEMBER 2010
REV. 1.1.3
GENERAL DESCRIPTION
The XR16L25501 (L2550) is a dual universal
asynchronous receiver and transmitter (UART). The
XR16L2550
is
an
improved
version
of
the
ST16C2550 UART with lower operating voltages and
5 volt tolerant inputs. The L2550 provides enhanced
UART functions with 16 byte FIFOs, a modem control
interface and data rates up to 4 Mbps. Onboard
status registers provide the user with error indications
and operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. Independent
programmable baud rate generators are provided to
select transmit and receive clock rates up to 3.125
Mbps. The Baud Rate Generator can be configured
for either crystal or external clock input. An internal
loopback capability allows onboard diagnostics. The
L2550 is available in a 44-pin PLCC, 48-pin TQFP
and 32-pin QFN packages. The L2550 is fabricated in
an advanced CMOS process.
NOTE: 1 Covered by U.S. Patent #5,649,122.
APPLICATIONS
Portable Appliances
Medical Monitors
Base Stations
Micro Servers
Telecommunication Network Routers
Industrial Automation Controls
FEATURES
2.25 to 5.5 Volt operation
5 Volt tolerant inputs
Pin-to-pin compatible to Exar’s ST16C2450,
ST16C2550 and XR16L2750 in 44-PLCC and 48-
TQFP packages
Pin-to-pin compatible to XR16C2850 in 44-PLCC
Pin
alike
XR16L2551,
XR16L2751
and
XR16C2850 in 48-TQFP package
Two independent UART channels
Up to 3.125Mbps with external clock of 50 MHz
Register Set compatible to 16C550
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable Receive FIFO interrupt trigger
levels
Automatic RTS/CTS hardware flow control
Automatic Xon/Xoff software flow control
Wireless infrared encoder/decoder
Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
Tiny 32-QFN, no lead package (5x5x0.9mm)
44-PLCC and 48-TQFP packages also available
FIGURE 1. XR16L2550 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
8-bit Data
Bus
Interface
UART Channel A
16 Byte TX FIFO
16 Byte RX FIFO
BRG
TX & RX
UART
Regs
2.25 to 5.5 Volt VCC
GND
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA#
CSB#
INTA
INTB
IOW#
IOR#
Reset
TXRDYA#
TXRDYB#
RXRDYA#
RDRXYB#
* 5 Volt Tolerant Inputs
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