參數(shù)資料
型號(hào)： XR16L2750
廠商： Exar Corporation
英文描述： 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
中文描述： 2.25V至5.5V的杜阿爾特64字節(jié)FIFO
文件頁數(shù)： 3/49頁
文件大小： 602K
代理商： XR16L2750
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
á
3
PIN DESCRIPTIONS
Pin Description
N
AME
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2:A0
29, 30, 31
26, 27, 28
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7:D0
9, 8, 7, 6, 5,
4, 3, 2
3, 2, 1, 48,
47, 46, 45,
44
19
I/O
Data bus lines [7:0] (bidirectional).
IOR#
24
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
20
15
I
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
16
10
I
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
CSB#
17
11
I
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
INTA
33
30
O
UART channel A Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output to a logic 0 when MCR[3] is set to a logic 1.
INTA is set to the three state mode and OP2A# to a logic 1 when
MCR[3] is set to a logic 0 (default). See MCR[3].
INTB
32
29
O
UART channel B Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output to a logic 0 when MCR[3] is set to a logic 1.
INTB is set to the three state mode and OP2B# to a logic 1 when
MCR[3] is set to a logic 0 (default). See MCR[3].
TXRDYA#
1
43
O
UART channel A Transmitter Ready (active low). The output
provides the TX FIFO/THR status for transmit channel A. See
Table 2
. If it is not used, leave it unconnected.
RXRDYA#
34
31
O
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
Table 2
. If it is not
used, leave it unconnected.
TXRDYB#
12
6
O
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
Table 2
. If it is not
used, leave it unconnected.
RXRDYB#
23
18
O
UART channel B Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel B. See
Table 2
. If it is not
used, leave it unconnected.
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