參數(shù)資料
型號: XR16L2750CJ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
中文描述: 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 34/49頁
文件大小: 602K
代理商: XR16L2750CJ
á
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
34
FCTR[6]: Scratchpad Swap
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
FCTR[7]: Programmable Trigger Register Select
Logic 0 = Registers TRG and FC selected for RX.
Logic 1 = Registers TRG and FC selected for TX.
4.19
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 15
). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
T
ABLE
15: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
EFR
BIT
-3
C
ONT
-3
EFR
BIT
-2
C
ONT
-2
EFR
BIT
-1
C
ONT
-1
EFR
BIT
-0
C
ONT
-0
T
RANSMIT
AND
R
ECEIVE
S
OFTWARE
F
LOW
C
ONTROL
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1, Xoff1
0
1
X
X
Transmit Xon2, Xoff2
1
1
X
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1, Xoff1
X
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
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