REV. 1.2.3 6 Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain" />
參數(shù)資料
型號(hào)： XR16L2751CM-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 47/50頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 64B DUAL 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.25 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤(pán)
其它名稱： 1016-1451
XR16L2751CM-F-ND
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.2.3
6
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
1.0 PRODUCT DESCRIPTION
The XR16L2751 (2751) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and
Transmitter (UART). Its features set is compatible to the XR16L2750 and XR16C2850 devices but offers Intel
or Motorola data bus interface and PowerSave to isolate the data bus interface during Sleep mode. Hence, the
2751 adds 4 more inputs: 16/68#, PwrSave, HDCNTl# and CLKSEL pins. Each UART is independently
controlled having its own set of device configuration registers. The configuration registers set is 16550 UART
compatible for control, status and data transfer. Additionally, each UART channel has 64-bytes of transmit and
receive FIFOs, automatic RTS/CTS hardware flow control with hysteresis control, automatic Xon/Xoff and
special character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level
counters, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate generator with a prescaler of
divide by 1 or 4. The XR16L2751 can operate from 2.25V to 5.5V with 5 volt tolerant inputs. The 2751 is
fabricated with an advanced CMOS process.
Enhanced Features
The 2751 DUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the ST16C2550, or one byte in the ST16C2450. The 2751 is designed to work with low supply
voltage and high performance data communication systems, that require fast data processing time. Increased
performance is realized in the 2751 by the larger transmit and receive FIFOs, FIFO trigger level control, FIFO
level counters and automatic flow control mechanism. This allows the external processor to handle more
networking tasks within a given time. For example, the ST16C2550 with a 16 byte FIFO, unloads 16 bytes of
receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at 115.2
Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with
the 64 byte FIFO in the 2751, the data buffer will not require unloading/loading for 6.1 ms. This increases the
service interval giving the external CPU additional time for other applications and reducing the overall UART
interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic hardware/
software flow control is uniquely provided for maximum data throughput performance especially when
operating in a multi-channel system. The combination of the above greatly reduces the CPU’s bandwidth
requirement, increases performance, and reduces power consumption.
The 2751 supports a half-duplex output direction control signaling pin, RTS# A/B, to enable and disable the
external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive
state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic
state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The
HDCNTL#
37
I
Auto RS-485 half-duplex direction output enable for channel A and B (active low).
Connect this pin to VCC for normal RTS# A/B function and to GND for auto RS-485
half-duplex direction output via the RTS# A/B pins. RTS# output goes low for transmit
and high for receive (polarity inversion is available via EMSR[3]). FCTR[3] in channel
A and B have control only if this input is disabled or at VCC.
RESET
(RESET#)
36
I
When 16/68# pin is HIGH for Intel bus interface, this input becomes RESET (active
high). When 16/68# pin is LOW for Motorola bus interface, this input becomes
RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all out-
puts of channel A and B. The UART transmitter output will be held HIGH, the receiver
input will be ignored and outputs are reset during reset period (see UART Reset Con-
ditions).
VCC
42
Pwr 2.25V to 5.5V power supply. All input pins, except XTAL1, are 5V tolerant.
GND
17
Pwr Power supply common, ground.
Pin Description
NAME
48-TQFP
PIN #
TYPE
DESCRIPTION
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