REV. 1.2.3 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 7 auto RS-485 direction control pin is not activated after reset. To a" />
參數(shù)資料
型號(hào): XR16L2751CM-F
廠商: Exar Corporation
文件頁數(shù): 48/50頁
文件大?。?/td> 0K
描述: IC UART FIFO 64B DUAL 48TQFP
標(biāo)準(zhǔn)包裝: 250
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.25 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
其它名稱: 1016-1451
XR16L2751CM-F-ND
XR16L2751
REV. 1.2.3
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
7
auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has
to set FCTR[3] = 1. This pin is normally high for receive state, low for transmit state.
Data Bus Interface, Intel or Motorola Type
The 2751 provides a single host interface for the 2 UARTs and supports Intel or Motorola microprocessor
(CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type
of CPUs using IOR#, IOW# and CSA# or CSB# inputs for data bus operation. The Motorola bus compatible
interface instead uses the R/W#, CS# and A3 signals for data bus transactions. Few data bus interface signals
change their functions depending on user’s selection, see pin description for details. The Intel and Motorola
bus interface selection is made through the pin, 16/68#, pin 24.
Data Rate
Each channel in the 2751 is capable of operation up to 3.125 Mbps at 5V, 2 Mbps at 3.3V and 1 Mbps at 2.5V
supply with 16X internal sampling clock rate, and 6.25 Mbps at 5V, 4 Mbps at 3.3V and 2 Mbps at 2.5V with 8X
sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and XTAL2, or
external clock source of up to 50 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a
software option, the user can set the prescaler bit for data rates of up to 1.84 Mbps.
Internal Enhanced Register Sets
Each UART has a set of enhanced registers providing control and monitoring functions for interrupt enable/
disable and status, FIFO enable/disable, programmable TX and RX FIFO trigger level, TX and RX FIFO level
counters, automatic hardware/software flow control enable/disable with selectable hysteresis, automatic RS-
485 half-duplex direction control output enable/disable, programmable baud rates, infrared encoder/decoder
enable/disable, modem interface controls and status, and sleep mode are all standard features. Following a
power on reset or an external reset (and operating in 16 or Intel Mode), the registers defaults to the reset
condition and its is compatible with previous generation of UARTs, 16C450, 16C550, 16C650A and 16C850.
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