參數(shù)資料
型號: XR16L2751CM
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
中文描述: 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁數(shù): 24/52頁
文件大小: 618K
代理商: XR16L2751CM
á
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
24
4.0
INTERNAL REGISTER DESCRIPTIONS
4.1
See “RECEIVER” on page 14.
4.2
Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 13.
4.3
Baud Rate Generator Divisors (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’.
See
“Programmable Baud Rate Generator” on page 11.
for more details.
Receive Holding Register (RHR) - Read- Only
Baud Rate Generator Divisor
0 0 0
DLL
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
LCR
0xBF
0 0 1
DLM
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0 0 0
DREV
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
LCR
0xBF
DLL=0x00
DLM=0x00
0 0 1
DVID
RD
0
0
0
0
1
0
1
0
Enhanced Registers
0 0 0
TRG
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR=0
X
BF
0 0 0
FC
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0 0 1
FCTR
RD/WR
RX/TX
Mode
SCPAD
Swap
Trig
Table
Bit-1
Trig
Table
Bit-0
Auto
RS485
Direction
Control
RX IR
Input
Inv.
Auto
RTS
Hyst
Bit-1
Auto
RTS
Hyst
Bit-0
0 1 0
EFR
RD/WR
Auto
CTS
Enable
Auto
RTS
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
1 0 0
XON1
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1
XON2
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0
XOFF1 RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1
XOFF2 RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
T
ABLE
9: INTERNAL REGISTERS DESCRIPTION.
S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1
A
DDRESS
A2-A0
R
EG
N
AME
R
EAD
/
W
RITE
B
IT
-7
B
IT
-6
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
C
OMMENT
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