參數(shù)資料
型號(hào): XR16L2752CJ
廠商: EXAR CORP
元件分類(lèi): 微控制器/微處理器
英文描述: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
中文描述: 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 5/49頁(yè)
文件大?。?/td> 619K
代理商: XR16L2752CJ
xr
REV. 1.2.0
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
5
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
CTSB#
28
I
UART channel B Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
DTRB#
27
O
UART channel B Data-Terminal-Ready (active low) or general purpose output. If this
pin is not used, leave it unconnected.
DSRB#
29
I
UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
CDB#
30
I
UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
RIB#
31
I
UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
MFB#
19
O
Multi-Function Output Channel B. This output pin can function as the OP2B#, BAUD-
OUTB#, or RXRDYB# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is LOW when MCR bit-
3 is set HIGH (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after a reset
or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data transfers.
See
Table 2 on page 8
for more details.
ANCILLARY SIGNALS
XTAL1
11
I
Crystal or external clock input. Caution: this input is not 5V tolerant.
XTAL2
13
O
Crystal or buffered clock output.
RESET
21
I
Reset (active high) - A longer than 40 ns HIGH pulse on this pin will reset the internal
registers and all outputs. The UART transmitter output will be held HIGH, the receiver
input will be ignored and outputs are reset during reset period (see External Reset
Conditions).
VCC
44, 33
Pwr
2.25 to 5.5V power supply. All input pins, except XTAL1, are 5V tolerant.
GND
22, 12
Pwr
Power supply common, ground.
Pin Description
N
AME
44-PLCC
P
IN
#
T
YPE
D
ESCRIPTION
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