REV. 1.4.2 PIN DESCRIPTIONS Pin Descriptions N
參數(shù)資料
型號: XR16L580IL24-F
廠商: Exar Corporation
文件頁數(shù): 34/49頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B 24QFN
標準包裝: 490
特點: *
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 2.25 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應商設備封裝: 24-QFN 裸露焊盤(4x4)
包裝: 托盤
XR16L580
4
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.4.2
PIN DESCRIPTIONS
Pin Descriptions
NAME
24-QFN
PIN#
32-QFN
PIN#
48-
TQFP
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
14
15
16
17
18
19
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the internal
registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
4
3
2
24
23
22
21
20
5
4
3
1
32
31
30
29
4
3
2
47
46
45
44
43
I/O
Data bus lines [7:0] (bidirectional).
IOR#
(NC)
13
14
19
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and this
input becomes read strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed by the address lines [A2:A0], puts the data byte on the data bus
to allow the host processor to read it on the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and
this input is not used.
IOW#
(R/W#)
11
12
16
I
When 16/68# pin is at logic 1, it selects Intel bus interface and this input
becomes write strobe (active low). The falling edge instigates the internal
write cycle and the rising edge transfers the data byte on the data bus to
an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and
this input becomes read (logic 1) and write (logic 0) signal.
CS#
7
8
11
I
This input is chip select (active low) to enable the device.
INT
(IRQ#)
17
20
30
O
(OD)
When 16/68# pin is at logic 1 for Intel bus interface, this output become
the active high device interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INT is set to the active mode
when MCR[3] is set to a logic 1. INT is set to the three state mode when
MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes the active low device interrupt output (open drain). An external
pull-up resistor is required for proper operation.
MODEM OR SERIAL I/O INTERFACE
TX
6
7
8
O
UART Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal
will be a logic 1 during reset or idle (no data). Infrared IrDA transmit and
receive interface is enabled when MCR[6] = 1. In the Infrared mode, the
inactive state (no data) for the Infrared encoder/decoder interface is a
logic 0. If it is not used, leave it unconnected.
RX
5
6
7
I
UART Receive Data or infrared receive data. Normal receive data input
must idle at logic 1 condition. The infrared receiver idles at logic 0.
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