REV. 1.4.2 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.2 5-Volt Tolerant Inputs The L580 can accept " />
參數(shù)資料
型號(hào)： XR16L580IL24-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 49/49頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 16B 24QFN
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422
電源電壓： 2.25 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 24-QFN 裸露焊盤(pán)（4x4）
包裝： 托盤(pán)
XR16L580
9
REV. 1.4.2
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
2.2
5-Volt Tolerant Inputs
The L580 can accept up to 5V inputs when operating at 3.3V or 2.5V. But note that if the L580 is operating at
2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial transceiver that
is operating at 5V. Note that the XTAL1 pin is not 5V tolerant when external clock supply is used.
2.3
Device Hardware Reset
The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to
their default state (see
Table 11). An active pulse of longer than 40 ns duration will be required to activate the
reset function in the device.
2.4
Device Identification and Revision
The XR16L580 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x01 to
indicate XR16L580 and reading the content of DLL will provide the revision of the part; for example, a reading
of 0x01 means revision A.
2.5
Internal Registers
The L580 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to those already available in the standard 16C550. These registers
function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control
register (FCR), receive line status and control registers, (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and an user accessible Scratchpad
register (SPR).
Beyond the general 16C550 features and capabilities, the L580 offers enhanced feature registers (EFR, Xon1,
Xoff 1, Xon1 and Xoff2) that provide automatic RTS and CTS hardware flow control and Xon/Xoff software flow
control. All the register functions are discussed in full detail later in
2.6
DMA Mode
The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the
RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the
XR16L580. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’.
2.7
INT (IRQ#) Output
The interrupt output changes according to the operating mode and enhanced features setup.
Table 2 below summarize the operating behavior for the transmitter and receiver in the Intel and Motorola
modes. Also see Figures
20 through 23.
TABLE 1: INT (IRQ#) PIN OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
(16/68# = 1)
0 = one byte in THR
1 = THR empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
IRQ# Pin
(16/68# = 0)
1 = one byte in THR
0 = THR empty
1 = FIFO above trigger level
0 = FIFO below trigger level or FIFO empty
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