參數(shù)資料
型號: XR16L784CVTR-F
廠商: Exar Corporation
文件頁數(shù): 17/51頁
文件大?。?/td> 0K
描述: IC UART FIFO 64B QUAD 64LQFP
標準包裝: 1,000
特點: *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
XR16L784
24
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
REV. 1.2.3
3.1.6
SLEEP [7:0] - (default 0x00)
The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power
consumption when the system needs to put the UART(s) to idle. The UART enters sleep mode when there is
no interrupt pending. When all 4 UARTs are put to sleep, the on-chip oscillator shuts off to further conserve
power. In this case, the quad UART is awakened by any of the UART channel on from a receive data byte or a
change on the modem port (CTS#, DSR#, CD# and RI#). The UART is ready after 32 crystal clocks to ensure
full functionality. Also, a special interrupt is generated with an indication of no pending interrupt. Reading INT0
will clear this wake-up interrupt. Logic 0 (default) and logic 1 disable and enable sleep mode respectively.
3.1.7
Device Identification and Revision
There are 2 internal registers that provide device identification and revision, DVID and DREV registers. The 8-
bit content in the DVID register provides device identification. A return value of 0x24 from this register indicates
the device is a XR16L784. The DREV register returns a 8-bit value of 0x01 for revision A, 0x02 for revision B
and so on. This information is very useful to the software driver for identifying which device it is communicating
with and to keep up with revision changes.
DVID [7:0] (default 0x24)
Device identification for the type of UART. The upper nibble indicates it is a XR16L78x series with lower nibble
indicating the number of channels.
Examples:
XR16L784 = 0x24
XR16L788 = 0x28
DREV [7:0]
Revision number of the XR16L784. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
3.1.8
REGB [7:0] - (default 0x00)
REGB register provides a control for simultaneous write to all 4 UARTs configuration registers or individually.
This is very useful for device intialization in the power up and reset routines.
REGB[0]
Logic 0 (default) write to each UART configuration registers individually.
Logic 1 enables simultaneous write to all 4 UARTs configuration register. Useful during device initializa-
tion.
REGB[7:1]
Reserved
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
SLEEP Register
Individual UART Channel Sleep Enable
Rsvd
Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
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