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參數(shù)資料
型號: XR16L784CVTR-F
廠商: Exar Corporation
文件頁數(shù): 23/51頁
文件大小: 0K
描述: IC UART FIFO 64B QUAD 64LQFP
標(biāo)準(zhǔn)包裝: 1,000
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
XR16L784
3
REV. 1.2.3
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
PIN DESCRIPTIONS
Pin Descriptions
NAME
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A7-A0
6-1,64,63
I
Address data lines [7:0]. A0:A3 selects individual UART’s 16 configuration
registers, A4:A6 selects UART channel 0 to 3, and A7 selects the global
device configuration registers
D7:D0
18-11
IO
Data bus lines (7:0] (bidirectional).
IOR#
7
I
When 16/68# pin is HIGH, it selects Intel bus interface and this input is read
strobe (active low). The falling edge instigates an internal read cycle and
retrieves the data byte from an internal register pointed by the address lines
[A7:A0], puts it on the data bus to allow the host processor to read it on the
leading edge.
When 16/68# pin is LOW, it selects Motorola bus interface and this input
should be connected to VCC.
IOW#
(R/W#)
8
I
When 16/68# pin is HIGH, it selects Intel bus interface and this input
becomes write strobe (active low). The falling edge instigates the internal
write cycle and the leading edge transfers the data byte on the data bus to an
internal register pointed by the address lines.
When 16/68# pin is LOW, it selects Motorola bus interface and this input
becomes read (logic 1) and write (logic 0) signal.
CS#
62
I
When 16/68# pin is HIGH, this input is chip select (active low) to enable the
XR16L784 device.
When 16/68# pin is LOW, this input becomes the read and write strobe
(active low) for the Motorola bus interface.
INT#
61
OD
Global interrupt output from XR16L784 (open drain, active low). This output
requires an external pull-up resistor (47K-100K ohms) to operate properly. It
may be shared with other devices in the system to form a single interrupt line
to the host processor and have the software driver polls each device for the
interrupt status.
MODEM OR SERIAL I/O INTERFACE
TX0
53
O
UART channel 0 Transmit Data or infrared transmit data. Normal TXD output
idles HIGH while infrared TXD output idles LOW.
RX0
60
I
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles HIGH while infrared RXD input idles LOW. In the infrared mode, the
polarity of the incoming RXD signal can be selected via FCTR bit-4. If this bit
is a logic 0, a LOW on the RXD input is considered a mark and if this bit is a
logic 1, a HIGH on the RXD input is considered a space.
RTS0#
55
O
UART channel 0 Request to Send or general purpose output (active low).
This port must be asserted prior using for one of two functions:
1) auto RTS flow control, see EFR bit-6, MCR bits-1 & 2, FCTR bits 0-3 and
IER bit-6
2) Auto RS485 half-duplex direction control, see FCTR bit-5, MCR bit-2 and
MSR bits 4-7.
CTS0#
59
I
UART channel 0 Clear to Send or general purpose input (active low). It can be
used for auto CTS flow control, see EFR bit-7, MCR bit-2 and IER bit-7.
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