參數(shù)資料
型號(hào)： XR16L784IV
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
中文描述： 4 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64
文件頁(yè)數(shù)： 10/52頁(yè)
文件大?。?/td> 625K
代理商： XR16L784IV
XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
á
REV. 1.2.0
10
2.7.3
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
Transmitter Operation in FIFO Mode
2.8
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timing. It verifies and validates every bit
on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an
internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of
the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer
is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO
trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt
when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-
4.6 character times. The RHR interrupt is enabled by IER bit-0.
Receiver
F
IGURE
6. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
F
IGURE
7. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X or 8X Clock
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Transmit
FIFO
16X or 8X Clock
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
TXFIFO1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16L784IV-F 功能描述:UART 接口集成電路 2.97V-5.5V 64B FIFO temp -45 to 85C RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16L784IVTR-F 功能描述:UART 接口集成電路 PCI BUS QUAD UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16L788 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE OCTAL UART
XR16L788_05 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
XR16L788_08 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
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