參數(shù)資料
型號： XR16L788IQ
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： HIGH PERFORMANCE OCTAL UART
中文描述： 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 20 MM, 3 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù)： 31/42頁
文件大?。?/td> 557K
代理商： XR16L788IQ
XR16L788 OCTAL UART
á
REV. 1.1.4
31
EFR BIT 0-3: Software Flow Control Select
Combinations of software flow control can be select-
ed by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the
functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5,
and MCR bits 5-7 to be modified. After modifying any
enhanced bits, EFR bit-4 can be set to a logic 0 to
latch the new values. This feature prevents legacy
software from altering or overwriting the enhanced
functions once set. Normally, it is recommended to
leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced fea-
tures. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are saved to retain the user settings.
After a reset, the IER bits 4-7, ISR bits 4-5, FCR
bits 4-5, and MCR bits 5-7 are set to a logic 0 to be
compatible with ST16C554 mode. (default).
Logic 1 = Enables the enhanced functions. When
this bit is set to a logic 1 all enhanced features are
enabled.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled.
(default)
Logic 1 = Special Character Detect Enabled. The
UART compares each incoming receive character
with data in Xoff-2 register. If a match exists, the
received data will be transferred to FIFO and ISR
bit-4 will be set to indicate detection of the special
character. Bit-0 corresponds with the LSB bit for the
receive character. If flow control is set for compar-
ing Xon1, Xoff1 (EFR [1:0]=10) then flow control
and special character work normally. However, if
flow control is set for comparing Xon2, Xoff2
(EFR[1:0]=01) then flow control works normally, but
Xoff2 will not go to the FIFO, and will generate an
Xoff interrupt and a special character interrupt.
EFR[6]: AUTO RTS OR DTR FLOW CONTROL
ENABLE
RTS#/DTR# output may be used for hardware flow
control by setting EFR bit-6 to logic 1. When Auto
RTS/DTR is selected, an interrupt will be generated
when the receive FIFO is filled to the programmed
trigger level and RTS/DTR# will de-assert to a logic 1
at the next upper trigger or selected hysteresis level.
RTS/DTR# will return to a logic 0 when FIFO data
falls below the next lower trigger or selected hystere-
sis level (see FCTR bits 4-7). The RTS# or DTR# out-
put must be asserted (logic 0) before the auto RTS/
DTR can take effect. The selection for RTS# or DTR#
is through MCR bit-2. RTS/DTR# pin will function as a
general purpose output when hardware flow control is
disabled.
Logic 0 = Automatic RTS/DTR flow control is dis-
abled. (default)
Logic 1 = Enable Automatic RTS/DTR flow control.
EFR[7]: Auto CTS Flow Control Enable
T
ABLE
14: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
EFR
BIT
-3
C
ONT
-3
EFR
BIT
-2
C
ONT
-2
EFR
BIT
-1
C
ONT
-1
EFR
BIT
-0
C
ONT
-0
T
RANSMIT
AND
R
ECEIVE
S
OFTWARE
F
LOW
C
ONTROL
0
0
1
0
1
X
X
X
1
0
0
0
1
1
X
X
X
0
0
X
X
X
X
0
1
0
1
0
X
X
X
X
0
0
1
1
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/ Xoff1,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2/Xoff2,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
1
1
1
1
1
1
1
0
0
1
1
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