參數(shù)資料
型號： XR16L788IQ
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： HIGH PERFORMANCE OCTAL UART
中文描述： 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 20 MM, 3 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù)： 9/42頁
文件大?。?/td> 557K
代理商： XR16L788IQ
XR16L788 OCTAL UART
á
REV. 1.1.4
9
1.1.1
The XR16L788 has a global interrupt source register
set that consists of 4 consecutive registers [INT0,
INT1, INT2 and INT3]. The four registers are in the
device configuration register address space.
The Global Interrupt Source Registers
All four registers default to logic zero (as indicated in
square braces) for no interrupt pending. All 8 channel
interrupts are enabled or disabled in each channel’s
IER register. INT0 shows individual status for each
channel while INT1, INT2 and INT3 show the details
of the source of each channel’s interrupt with its
unique 3-bit encoding.
Figure 4
shows the 4 interrupt
registers in sequence for clarity. The 16-bit timer and
sleep wake-up interrupts are masked in the device
configuration registers,
TIMERCNTL and SLEEP.
An in-
terrupt is generated (if enabled) by the 788 when
awakened from sleep if all 8 channels were placed in
the sleep mode previously.
Each bit gives an indication of the channel that has
INT0 C
HANNEL
I
NTERRUPT
I
NDICATOR
:
requested for service. For example, bit-0 represents
channel 0 and bit-7 indicates channel 7. Logic one in-
dicates the channel N [7:0] has called for service. The
interrupt bit clears after reading the appropriate regis-
ter of the interrupting UART channel register (ISR,
LSR and MSR). See Table 9 for interrupt clearing de-
tails.
INT1, INT2
AND
INT3 I
NTERRUPT
S
OURCE
L
OCATOR
INT3, INT2 and INT1 provide a 24-bit (3 bits per
channel) encoded interrupt indicator. Table 3 shows
the 3 bit encoding and their priority order. The 16-bit
Timer time-out interrupt will show up only as a chan-
nel 0 interrupt. For other channels, interrupt 7 is re-
served.
.
INT3
[0x00]
INT2
[0x00]
INT1
[0x00]
INT0
[0x00]
INT0 Register
Individual UART Channel Interrupt Status
Ch-7
Ch-6
Ch-5
Ch-4
Ch-3
Ch-2
Ch-1
Ch-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
F
IGURE
4. T
HE
G
LOBAL
I
NTERRUPT
R
EGISTERS
, INT0, INT1, INT2
AND
INT3
Channel-7
Channel-6
Channel-5
Channel-4
Channel-3
Channel-2
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
INT0 Register
Ch-4
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Ch-6
Ch-7
Ch-5
Ch-
3
Ch-
2
Ch-1
Ch-0
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