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參數(shù)資料
| 型號： | XR16M554IV80-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 16/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B QUAD 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 119 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232 |
| 電源電壓： | 1.62 V ~ 3.63 V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（12x12） |
| 包裝： | 托盤 |
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XR16M554/554D
23
REV. 1.0.0
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the
DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY and RXRDY pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Reserved (Default 0)
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections.
TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR BIT-7
FCR BIT-6
RECEIVE TRIGGER LEVEL
0
1
0
1
0
1
4
8
14
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| XR16M564 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO |
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