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參數(shù)資料
型號(hào)： XR16M580IM48-0A-EB
廠商： Exar Corporation
文件頁數(shù)： 22/56頁
文件大小： 0K
描述： EVAL BOARD FOR XR16M580-A 48TQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16M580
29
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
Special character interrupt is cleared by a read to ISR register or after next character is received. See
EMSR[7].
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
Wakeup interrupt is cleared by a read to ISR register.
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 8).
ISR[4]: Interrupt Status (requires EFR bit-4 = 1)
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff, Xon or special character(s).
ISR[5]: Interrupt Status (requires EFR bit-4 = 1)
ISR bit-5 indicates that CTS# or RTS# has changed state from LOW to HIGH.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Receive Data Time-out)
3
0
1
0
RXRDY (Received Data Ready)
4
0
1
0
TXRDY (Transmit Ready)
5
0
MSR (Modem Status Register)
6
0
1
0
RXRDY (Received Xon, Xoff or Special character)
7
1
0
CTS#, RTS# change of state
-
0
1
None (default) or Wakeup interrupt
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