參數資料
型號： XR16M654IV-0B-EVB
廠商： Exar Corporation
文件頁數： 13/58頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR16M654-B 64LQFP
標準包裝： 1
系列： *
XR16M654/654D
20
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.0
2.11
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 12):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the RTS#
pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.12
Auto RTS Hysteresis
The M654 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the selected RX trigger level. The RTS# pin will not be forced
HIGH (RTS off) until the receive FIFO reaches one trigger level above the selected trigger level in the trigger
table (Table 12). The RTS# pin will return LOW after the RX FIFO is unloaded to one level below the selected
trigger level. Under the above described conditions, the M654 will continue to accept data until the receive
FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is asserted LOW (RTS On).
FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
TABLE 7: AUTO RTS (HARDWARE) FLOW CONTROL
RX TRIGGER LEVEL
INT PIN ACTIVATION
RTS# DE-ASSERTED (HIGH)
(CHARACTERS IN RX FIFO)
RTS# ASSERTED (LOW)
(CHARACTERS IN RX FIFO)
8
16
0
16
56
8
56
60
16
60
56
Rece ive Da ta S hift
R egister (R S R )
R X FIFO 1
16X or 8X o r 4X C lock
( DLD[5:4] )
Err
o
rT
a
g
s
(64
-s
e
ts)
Er
ro
rT
a
g
s
i
n
LS
R
b
its
4:
2
R ece ive D ata C haracte rs
D a ta B it
V alidation
Receive
D ata FIF O
Receive
Data
Rece ive Da ta
B yte and E rrors
R H R Interrupt (IS R bit-2 ) prog ram m ed for
de sired FIFO trigger level.
FIFO is E nab led by F C R b it-0=1
R TS # de -asserts w hen data fills abo ve the flo w
con trol trig ger le vel to su spend rem o te tran sm itter.
E na ble by E FR b it-6=1, M C R bit-1.
R TS# re-asserts w he n data falls be low the flow
contro l trigge r level to resta rt rem o te tran sm itter.
E na ble by E FR b it-6=1, M C R bit-1.
64 bytes by 11-bit w ide
FIFO
Trigger=16
D ata falls to
8
D ata fills to
56
E xam ple
: - R X FIFO trigger level selected at 16 bytes
(See N ote Below )
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