REV. 1.0.2 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO EMSR[5:4]: Extended RTS Hysteresis T
參數(shù)資料
型號(hào)： XR16M770IL32-0B-EB
廠(chǎng)商： Exar Corporation
文件頁(yè)數(shù)： 31/52頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR16M770-B 32QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16M770
37
REV. 1.0.2
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
EMSR[5:4]: Extended RTS Hysteresis
TABLE 13: AUTO RTS HYSTERESIS
BIT-5
BIT-4
BIT-1
BIT-0
HYSTERESIS
(CHARACTERS)
0
1
0
1
0
1
0
±4
±6
±8
0
1
0
1
0
1
0
1
±8
±16
±24
±32
1
0
1
0
1
0
1
±40
±44
±48
±52
1
0
1
0
1
0
1
±12
±20
±28
±36
EMSR[6]: LSR Interrupt Mode
Logic 0 = LSR Interrupt Delayed (default). LSR bits 2, 3, and 4 will generate an interrupt when the character
with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
EMSR[7]: Xoff/Special character Interrupt Mode Select
This bit selects how the Xoff and Special character interrupt is cleared. The XON interrupt can only be cleared
by reading the ISR register.
Logic 0 = Xoff interrupt is cleared by either reading ISR register or when an XON character is received.
Special character interrupt is cleared by either reading ISR register or when next character is received.
(default).
Logic 1 = Xoff/Special character interrupt can only be cleared by reading the ISR register.
4.13
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
These registers make-up the value of the baud rate divisor. The M770 has different DLL, DLM and DLD for
transmitter and receiver. It provides more convenience for the transmitter and receiver to transmit data with
different rate. The M770 uses DLD[7:6] to select TX or RX. Then it provides DLD[5:0] to select the sampling
frequency and fractional baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit
divisor value. The value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See Table 14 below and See ”Section 2.7, Programmable
EMSR
FCTR
RTS#
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