REV. 1.0.3 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO FIGURE 7. T
參數(shù)資料
型號： XR16V2550IM-F
廠商： Exar Corporation
文件頁數(shù)： 5/46頁
文件大?。?/td> 0K
描述： IC UART FIFO 16B 48TQFP
標準包裝： 250
特點： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422
電源電壓： 2.25 V ~ 3.6 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 1016-1464
1016-1464-ND
1016-1648
XR16V2550IM-F-ND
XR16V2550
13
REV. 1.0.3
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Transmit
FIFO
16X or 8X or 4X Clock
(DLD[5:4])
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.)
TXFIFO1
2.12
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD[5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0. See Figure 8 and Figure 9 below.
2.12.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16V2550IMTR-F 制造商:Exar Corporation 功能描述:UART 2-CH 16Byte FIFO 2.5V/3.3V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16V2550IMTR-F
XR16V2551 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
XR16V2551_07 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
XR16V2551IL 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
XR16V2551IL-0B-EB 功能描述:UART 接口集成電路 Supports V2551 32pin QFN, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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