FIGURE 8. RECEIVER O
參數(shù)資料
型號(hào): XR16V2550IM-F
廠商: Exar Corporation
文件頁(yè)數(shù): 6/46頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 16B 48TQFP
標(biāo)準(zhǔn)包裝: 250
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤(pán)
其它名稱(chēng): 1016-1464
1016-1464-ND
1016-1648
XR16V2550IM-F-ND
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO 1
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Error
T
a
gs
(16-
sets)
E
rro
rT
ag
si
n
LSR
bi
ts
4:
2
Receive Data Characters
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
16 bytes by 11-bit wide
FIFO
Trigger=8
Data falls to
4
Data fills to
14
Example
: - RX FIFO trigger level selected at 8 bytes
(See Note Below)
XR16V2550
14
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
REV. 1.0.3
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