FIGURE 2. PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
63
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
DTRB#
CTSB#
DSRB#
CDB
#
RIB
#
RX
B
VC
C
16
/68#
A2
A1
A0
XT
A
L1
XT
A
L2
RE
S
E
T
RX
RDY
#
T
X
RDY
#
GN
D
RX
C
RI
C#
CDC
#
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
DSRC#
CDA
#
RI
A
#
RX
A
GN
D
D7
D6
D5
D4
D3
D2
D1
D0
IN
T
S
E
L
VC
C
RX
D
RID#
CD
D#
XR16V554
68-pin PLCC
Intel Mode
(16/68# pin connected to VCC)
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
63
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DSRA#
CTSA#
DTRA#
VCC
RTSA#
IRQ#
CS#
TXA
R/W#
TXB
A3
N.C.
RTSB#
GND
DTRB#
CTSB#
DSRB#
CD
B
#
RI
B#
RX
B
VC
C
16
/68#
A2
A1
A0
XTAL
1
XTAL
2
RESET
R
X
RDY#
T
X
RDY#
GND
RXC
RI
C#
CDC#
DSRD#
CTSD#
DTRD#
GND
RTSD#
N.C.
TXD
N.C.
TXC
A4
N.C.
RTSC#
VCC
DTRC#
CTSC#
DSRC#
CDA#
RI
A
#
RX
A
GN
D
D7
D6
D5
D4
D3
D2
D1
D0
GND
VC
C
RX
D
RI
D
#
C
DD#
XR16V554
68-pin PLCC
Motorola Mode
(16/68# pin connected to GND)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
DS
RB
#
CD
B
#
RI
B
#
RX
B
VC
C
A2
A1
A0
XT
AL
1
XTA
L
2
R
ESE
T
GN
D
RX
C
RI
C#
CD
C#
DSRC
#
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
CD
A
#
RI
A#
RX
A
GN
D
D7
D6
D5
D4
D3
D2
D1
D0
VC
C
RX
D
RI
D
#
CDD
#
XR16V554/554D
64-pin TQFP
Intel Mode Only
XR16V554/554D
2
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
REV. 1.0.3