REV. 1.0.3 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16V554 (V554) integrates the functions of 4 " />
參數(shù)資料
型號(hào)： XR16V554IV80-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 43/43頁(yè)
文件大小： 0K
描述： IC UART FIFO 16B QUAD 80LQFP
標(biāo)準(zhǔn)包裝： 119
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 16 字節(jié)
規(guī)程： RS232
電源電壓： 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（12x12）
包裝： 托盤(pán)
其它名稱： 1016-1570-5
XR16V554IV80-F-ND
XR16V554/554D
9
REV. 1.0.3
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
1.0 PRODUCT DESCRIPTION
The XR16V554 (V554) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled and has its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 16 bytes of transmit and receive FIFOs, programmable baud rate
generator and data rate up to 4 Mbps at 3.3 V. The XR16V554 can operate from 2.25 to 3.6 volts. The V554 is
fabricated with an advanced CMOS process.
Enhanced FIFO
The V554 QUART provides a solution that supports 16 bytes of transmit and receive FIFO memory, instead of
one byte in the ST16C454. The V554 is designed to work with high performance data communication systems,
that require fast data processing time. Increased performance is realized in the V554 by the larger transmit and
receive FIFOs and Receiver FIFO trigger level control. This allows the external processor to handle more
networking tasks within a given time. This increases the service interval giving the external CPU additional time
for other applications and reducing the overall UART interrupt servicing time.
Data Bus Interface, Intel or Motorola Type
The V554 provides a single host interface for the 4 UARTs and supports Intel or Motorola microprocessor
(CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type
of CPUs using IOR#, IOW# and CSA#, CSB#, CSC# or CSD# inputs for data bus operation. The Motorola bus
compatible interface instead uses the R/W#, CS#, A3 and A4 signals for data bus transactions. Few data bus
interface signals change their functions depending on user’s selection, see pin description for details. The Intel
and Motorola bus interface selection is made through the pin 16/68#.
Data Rate
The V554 is capable of operation up to 4 Mbps at 3.3V. The device can operate at 3.3V with a crystal oscillator
of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of 64 MHz on XTAL1 pin. With a
typical crystal of 14.7456 MHz and through a software option, the user can set the sampling rate for data rates
of up to 921.6 Kbps.
Enhanced Features
The rich feature set of the V554 is available through the internal registers. Selectable receive FIFO trigger
levels, programmable baud rates, infrared encoder/decoder interface and modem interface controls are all
standard features. In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software controlled or
continuous interrupt capability. For backward compatibility to the ST16C554, the 64-pin LQFP does not have
the INTSEL pin. Instead, two different LQFP packages are offered. The XR16V554DIV operates in the
continuous interrupt enable mode by internally bonding INTSEL to VCC. The XR16V554IV operates in
conjunction with MCR bit-3 by internally bonding INTSEL to GND.
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