參數(shù)資料
型號(hào): XR16V654IL-F
廠商: Exar Corporation
文件頁(yè)數(shù): 10/58頁(yè)
文件大小: 0K
描述: IC UART FIFO 64B QUAD 48QFN
標(biāo)準(zhǔn)包裝: 260
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS232
電源電壓: 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 托盤(pán)
其它名稱: 1016-1468
XR16V654IL-F-ND
XR16V654/654D
18
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.1
2.9.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
2.9.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
FIGURE 8. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 9. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X or 8X or 4X
Clock
( DLD[5:4] )
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Transmit
FIFO
16X or 8X or 4X Clock
(DLD[5:4])
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.)
TXFIFO1
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