參數(shù)資料
型號(hào)： XR16V698IQ-0A-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 27/58頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR XR16V698-A 100QFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16V698
33
REV. 1.0.3
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
LOW to HIGH.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when RTS# pin makes a transition from
LOW to HIGH.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[4]: Reserved
IER[3]: Modem Status Interrupt Enable
The Modem Status Register interrupt is issued whenever any of the delta bits of the MSR register (bits 3:0) is
set.
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[2]: Receive Line Status Interrupt Enable
An Overrun error, Framing error, Parity error or detection of a Break character will result in an LSR interrupt.
The 698 will issue an LSR interrupt immediately after receiving a character with an error. It will again re-issue
the interrupt (if the first one has been cleared by reading the LSR register) when the character with the error is
on the top of the FIFO, meaning the next one to be read out of the FIFO.
For example, let’s consider an incoming data stream of 0x55, 0xAA, etc and that the character 0xAA has a
Parity error associated with it. Let’s assume that the character 0x55 has not been read out of the FIFO yet. The
698 will issue an interrupt as soon as the stop bit of the character 0xAA is received. The LSR register will have
only the FIFO error bit (bit-7) set and none of the other error bits (Bits 1,2,3 and 4) will be set, since the byte on
the top of the FIFO is 0x55 which does not have any errors associated with it. When this byte has been read
out, the 698 will issue another LSR interrupt and this time the LSR register will show the Parity bit (bit-2) set.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[1]: TX Ready Interrupt Enable
In non-FIFO mode, a TX interrupt is issued whenever the THR is empty. In the FIFO mode, an interrupt is
issued twice: once when the number of bytes in the TX FIFO falls below the programmed trigger level and
again when the TX FIFO becomes empty. When auto RS-485 mode is enabled (FCTR bit-5 = 1), the second
interrupt is delayed until the transmitter (both the TX FIFO and the TX Shift Register) is empty.
Logic 0 = Disable Transmit Ready Interrupt (default).
Logic 1 = Enable Transmit Ready Interrupt.
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