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參數(shù)資料
| 型號： | XR17V252IM-0A-EVB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 35/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR17V252 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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XR17V252
40
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.2
5.4.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR bit [0] equals a logic 1 for FIFO enable; resetting IER bits [3:0] enables the XR16V252 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either can be used
in the polled mode by selecting respective transmit or receive control bit(s).
A.
LSR BIT-0 indicates there is data in RHR (non-FIFO mode) or RX FIFO (FIFO mode).
B.
LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C.
LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D.
LSR BIT-5 indicates THR (non-FIFO mode) or TX FIFO (FIFO mode) is empty.
E.
LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F.
LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit [4]=1)
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
LOW to HIGH.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit [4]=1)
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when RTS# pin makes a transition from
LOW to HIGH.
IER[5]: Xoff Interrupt Enable (requires EFR bit [4]=1)
Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[4]: Reserved
.
IER[3]: Modem Status Interrupt Enable
The Modem Status Register interrupt is issued whenever any of the delta bits of the MSR register (bits [3:0]) is
set.
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[2]: Receive Line Status Interrupt Enable
An Overrun error, Framing error, Parity error or detection of a Break character will result in an LSR interrupt.
The V252 will issue an LSR interrupt immediately after receiving a character with an error. It will again re-issue
the interrupt (if the first one has been cleared by reading the LSR register) when the character with the error is
on the top of the FIFO, meaning the next one to be read out of the FIFO.
For example, let’s consider an incoming data stream of 0x55, 0xAA, etc. and that the character 0xAA has a
Parity error associated with it. Let’s assume that the character 0x55 has not been read out of the FIFO yet. The
V252 will issue an interrupt as soon as the stop bit of the character 0xAA is received. The LSR register will
have only the FIFO error bit (bit [7]) set and none of the other error bits (bits [4:1]) will be set, since the byte on
the top of the FIFO is 0x55 which does not have any errors associated with it. When this byte has been read
out, the V252 will issue another LSR interrupt and this time the LSR register will show the Parity bit (bit [2]) set.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17V252IM-F | 功能描述:UART 接口集成電路 66MHz Dual PCI UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17V252IMTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 64Byte FIFO 3.3V 100-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR17V252IMTR-F |
| XR17V254 | 制造商:EXAR 制造商全稱:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT |
| XR17V254_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT |
| XR17V254IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT |
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