XR19L202
46
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
FIGURE 19. RECEIVE READY INTERRUPT TIMING [FIFO MODE]
FIGURE 20. TRANSMIT READY INTERRUPT TIMING [FIFO MODE]
RX
INT
D0:D7
S
T
SSR
RXINTDMA#
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
SSI
IOR#
T
RRI
(Reading data out
of RX FIFO)
TX
INT*
TX INT
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TX FIFO
Empty
T
S
T
SI
ISR is read
IER[1]
enabled
ISR is read
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.