參數(shù)資料
型號： XR19L202IL48-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 9/50頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR19L202 48QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR19L202
17
REV. 1.0.1
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
2.15
Sleep Modes and Power-Save Feature with Wake-Up Interrupt
There are three levels of power management integrated in the L202. The device is low power with low
operational and standby supply currents. In the Partial Sleep mode, the internal oscillator of the UART or
charge pump of the RS-232 transceiver is turned off to reduce the power consumption. In the Full Sleep mode,
both the oscillator and the charge pump are turned off. The Power-save mode provides additional power
saving by isolating the UART address, data and control signals during Sleep mode to minimize the power
consumption.
2.15.1
Partial Sleep Mode
There are two different partial sleep modes. In the first mode, the UART is in sleep mode and the charge pump
is active. In the other mode, the UART is still active but the charge pump is turned off.
2.15.1.1
UART in sleep mode, RS-232 transceiver active
If the ACP pin is LOW, then the charge pump for the RS-232 transceiver will always be active. But the UART
portion in the L202 can still enter sleep mode if all of these conditions are satisfied:
■ no interrupts pending (ISR bit-0 = 1)
■ the 16-bit divisor programmed in DLM and DLL registers is a non-zero value
■ sleep mode is enabled (IER bit-4 = 1)
■ modem inputs are not toggling (MSR bits 0-3 = 0)
■ RXD input pin is idling LOW
The L202 stops its crystal oscillator to conserve power in this mode. The user can check the XTAL2 pin for no
clock output as an indication that the device has entered the partial sleep mode.
The UART portion in the L202 resumes normal operation or active mode by any of the following:
■ a receive data start bit transition on the RXD input (LOW to HIGH)
■ a data byte is loaded to the transmitter, THR or FIFO
■ a change of logic state on any of the modem or general purpose serial inputs: i.e., any of the MSR bits 0-
3 shows a ’1’
If the sleep mode is enabled and the L202 is awakened by one of the conditions described above, an interrupt
is issued by the L202 to signal to the CPU that it is awake. The lower nibble of the interrupt source register
(ISR) will read a value of 0x1 for this interrupt and reading the ISR clears this interrupt. Since the same value
(0x1) is also used to indicate no pending interrupt, users should exercise caution while using the sleep mode.
The UART portion in the L202 will return to the sleep mode automatically after all interrupting conditions have
been serviced and cleared. If the UART portion of the L202 is awakened by the modem inputs, a read to the
MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an interrupt
is pending. The UART portion of the L202 will stay in the sleep mode of operation until it is disabled by setting
IER bit-4 to a logic 0.
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