參數(shù)資料
型號(hào): XR20M1172G28-0A-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 17/55頁(yè)
文件大小: 0K
描述: EVAL BOARD FOR XR20M1172 28TSSOP
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
嵌入式:
已用 IC / 零件: XR20M1172
主要屬性: 2 通道
次要屬性: I²C & SPI 接口
已供物品:
其它名稱: 1016-1622
XR20M1172G28-0A-EB-ND
XR20M1172
24
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.2.0
2.17
Internal Loopback
The M1172 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 19 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored.
Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the
UART may detect and report a false “break” signal. Also, Auto RTS/CTS flow control is not supported during
internal loopback.
FIGURE 19. INTERNAL LOOP BACK
TX
R X
M
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m
/
G
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e
ra
l
P
u
rp
o
s
e
C
o
n
tr
o
l
L
o
g
ic
In
te
rn
a
l
D
a
ta
B
u
s
L
in
e
s
a
n
d
C
o
n
tr
o
l
S
ig
n
a
ls
R TS #
MC R bit-4=1
V CC
VC C
Transm it Shift Register
(THR /FIFO )
Receive Shift Register
(RHR/FIFO )
C TS #
D TR#
D SR#
R I#
C D#
O P 1#
RTS#
CTS#
DTR#
DSR #
RI#
CD#
VCC
O P 2#
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