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參數(shù)資料
| 型號： | XR20M1172G28-0A-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 9/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR20M1172 28TSSOP |
| 標準包裝： | 1 |
| 主要目的： | 接口，UART |
| 嵌入式： | 否 |
| 已用 IC / 零件： | XR20M1172 |
| 主要屬性： | 2 通道 |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板 |
| 其它名稱： | 1016-1622 XR20M1172G28-0A-EB-ND |
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XR20M1172
17
REV. 1.2.0
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
2.8
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0.
2.8.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
The Non-FIFO mode is enabled by default for 16450 compatibility. For normal operation, the FIFO Mode must
be enabled.
FIGURE 15. RECEIVER OPERATION IN NON-FIFO MODE
R e ce ive D a ta S hift
R eg iste r (R SR )
R ece ive
D a ta B yte
a n d E rro rs
R H R In terrup t (IS R b it-2 )
R e ceive D ata
H olding R e gister
(R H R)
R X FIF O 1
1 6X o r 8X o r 4 X C lock
( D L D[5:4 ] )
R ece ive D ata C haracte rs
D a ta B it
V a lid ation
E rror
Ta gs in
LS R b its
4:2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR20M1172G28-0B-EB | 功能描述:界面開發(fā)工具 Supports M1172 28 ld TSSOP, SPI Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR20M1172IG28 | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR20M1172IG28-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR20M1172IG28-F | 制造商:Exar Corporation 功能描述:IC DUAL UART 16MBPS 3.63V 28-TSSOP 制造商:Exar Corporation 功能描述:IC, DUAL UART, 16MBPS, 3.63V, 28-TSSOP |
| XR20M1172IG28TR-F | 功能描述:UART 接口集成電路 1.8V 2 Ch 64-byte I2C/SPI UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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