REV. 1.0.0 1.21 Internal Loopback The M1280 UART provi" />
參數(shù)資料
型號: XR20M1280IL32-F
廠商: Exar Corporation
文件頁數(shù): 19/63頁
文件大?。?/td> 0K
描述: IC UART I2C/SPI 128 BYTE 32QFN
產(chǎn)品培訓(xùn)模塊: UART Product Overview
XR21V141x Full-Speed USB UART Family
標(biāo)準(zhǔn)包裝: 490
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
其它名稱: 1016-1386
XR20M1280
26
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
1.21
Internal Loopback
The M1280 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 20 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,
DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else
upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 20. INTERNAL LOOPBACK
TX
RX
M
ode
m
/
G
ene
ra
lP
u
rpose
Control
L
ogi
c
Inte
rnal
D
a
ta
Bus
Line
sand
Control
S
ignals
RT S #
M C R bit-4=1
VC C
T ra n sm it S h ift R e g is te r
(TH R /FIFO )
R ec e iv e S h ift R e gis ter
(RHR/F IF O )
CT S #
DT R#
DS R#
RI#
CD#
OP 1 #
RT S #
CT S #
DT R#
DS R#
RI#
CD #
VC C
OP 2 #
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