REV. 1.0.0 3.11 Special Function Register (SFR) - Write On" />
參數(shù)資料
型號(hào): XR20M1280IL32-F
廠商: Exar Corporation
文件頁(yè)數(shù): 37/63頁(yè)
文件大?。?/td> 0K
描述: IC UART I2C/SPI 128 BYTE 32QFN
產(chǎn)品培訓(xùn)模塊: UART Product Overview
XR21V141x Full-Speed USB UART Family
標(biāo)準(zhǔn)包裝: 490
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(pán)(5x5)
包裝: 托盤(pán)
其它名稱(chēng): 1016-1386
XR20M1280
42
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
3.11
Special Function Register (SFR) - Write Only
This register provides access to some of the advanced features of XR20M1280.
SFR[0]: Enable GPIO Registers (Requires EFR[4] = 1)
Logic 0 = GPIO control and status registers are not enabled.
Logic 1 = GPIOLVL register is accessible at SPR register location. GPIOINT, GPIO3T, GPIOINV, GPIOSEL
registers are accessible at XON1, XON2, XOFF1, and XOFF2 register locations.
SFR[1]: GPIO[15:8] or GPIO[7:0] Select (Requires EFR[4] = 1)
Logic 0 = GPIOLVL, GPIOINT, GPIO3T, GPIOINV and GPIOSEL registers will control and report the status
of GPIO[7:0].
Logic 1 = GPIOLVL, GPIOINT, GPIO3T, GPIOINV and GPIOSEL registers will control and report the status
of GPIO[15:8].
SFR[2]: GPIO Interrupt Enable (Requires EFR[4] = 1)
Logic 0 = GPIO interrupt is disabled.
Logic 1 = GPIO interrupt is enabled. GPIOs that have been configured as inputs can generate GPIO
interrupts if the bit is enabled in the GPIOINT register. The polarity of the GPIO interrupt is selected via the
GPIOINV register.
SFR[3]: Enable/Disable fast IR mode (Requires EFR[4] = 1)
The M1280 supports the new fast IR transmission with data rate up to 1.152 Mbps.
Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps (default).
Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps. For more IR mode information, please
SFR[4]: Enable/Disable Transmitter (Requires EFR[4] = 1)
Logic 0 = Enable Transmitter (default).
Logic 1 = Disable Transmitter.
SFR[5]: Enable/Disable Receiver (Requires EFR[4] = 1)
Logic 0 = Enable Receiver (default).
Logic 1 = Disable Receiver.
SFR[6]: Enable/Disable 9-bit mode (Requires EFR[4] = 1)
Logic 0 = Normal 8-bit mode (default).
Logic 1 = Enable 9-bit or Multidrop mode.
SFR[7]: TX Address Bit (Requires EFR[4] = 1)
This bit requires that forced "0" parity is enabled (LCR[5:3]=’111’). If this bit is enabled, the 9th bit of the next
byte written to THR will be a ’1’. This bit resets after a write to THR. For the 9-bit mode information, See
Logic 0 = Value of 9th bit will be ’0’ (default).
Logic 1 = Value of 9th bit will be ’1’.
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