REV. 1.4.0 FIGURE 3. N
參數(shù)資料
型號(hào)： XR21V1410IL16-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 29/30頁(yè)
文件大小： 0K
描述： IC UART FIFO USB SGL 16QFN
產(chǎn)品培訓(xùn)模塊： UART Product Overview
XR21V141x Full-Speed USB UART Family
產(chǎn)品變化通告： XR21V1410IL16-F Packing Change 26/Jan/2011
特色產(chǎn)品： XR21V141x Full-Speed USB UART
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 128 字節(jié)，384 字節(jié)
規(guī)程： USB 2.0
電源電壓： 2.97 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 16-QFN-EP（3x3）
包裝： 散裝
配用： 1016-1299-ND - EVAL BOARD FOR XR21V1410IL
其它名稱： 1016-1300
XR21V1410
8
1-CH FULL-SPEED USB UART
REV. 1.4.0
FIGURE 3. NORMAL OPERATION RECEIVE DATA FORMAT
1.5.2.3
Wide mode receive operation with 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received
data. The second byte consists of the error bits and break status. Wide mode receive data format is shown in
Figure 4.
1.5.2.4
Wide mode receive operation with 9-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the first 8 bits of
the received data. The 9th bit received is stored in the bit 0 of the second byte. The parity bit is not received /
checked. The remainder of the 2nd byte consists of the framing and overrun error bits and break status.
FIGURE 4. WIDE MODE RECEIVE DATA FORMAT
Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags
are historical flags indicating that an error has occurred since the previous request. Therefore, no conclusion
can be drawn as to which specific byte(s) may have contained an actual error in this manner.
1.5.3
Rx FIFO Low Latency
In normal operation all bulk-in transfers will be of maxPacketSize (64) bytes to improve throughput and to
minimize host processing. When there are 64 bytes of data in the RX FIFO, the V1410 will acknowledge a
bulk-in request from the host and transfer the data packet. If there is less than 64 bytes in the RX FIFO, the
V1410 may NAK the bulk-in request indicating that data is not ready to transfer at that time. However, if there
is less than 64 bytes in the RX FIFO and no data has been received for more than 3 character times, the
V1410 will acknowledge the bulk-in request and transfer any data in the RX FIFO to the USB host.
In some cases, especially when the baud rate is low, this increases latency unacceptably. The V1410 has a
low latency register bit that will cause the V1410 to immediately transfer any received data in the RX FIFO to
1
ST byte
7, 8, or 9bit data
7 6 5 4 3 2 1 0
7=‘0’ in7bit mode
1st byte
2nd byte
9 bit mode
7
6
5
4
3
2
1
0
x
O F B P
1st byte
B = Break
F = Framing Error
O = Overrun Error
2nd byte
7 or 8 bit mode
P = Parity Error (= ‘0’ if not enabled)
7 = ‘0’ in 7 bit mode
x = ‘0’
7
6
5
4
3
2
1
0
x
O F B 8
B = Break
F = Framing Error
O = Overrun Error
x = ‘0’
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