REV. 1.3.0 3.0 REGISTER SET DESCRIPTION The internal register set of the V1414 consists of 3 different bl" />
參數(shù)資料
型號(hào)： XR21V1414IM-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 10/34頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR21V1414
產(chǎn)品培訓(xùn)模塊： UART Product Overview
XR21V141x Full-Speed USB UART Family
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，USB 2.0 至 UART
嵌入式： 否
已用 IC / 零件： XR21V1414IM
已供物品： 板
其它名稱： 1016-1427
XR21V1414
18
4-CH FULL-SPEED USB UART
REV. 1.3.0
3.0
REGISTER SET DESCRIPTION
The internal register set of the V1414 consists of 3 different blocks of registers: the UART Manager, UART
registers and UART miscellaneous registers. The UART Manager controls the TX and RX enables and FIFOs
of all UART channels. The UART registers configure and control the remaining UART channel functionality
with the exception of low latency mode, wide mode and custom interrupt packet enables in the UART custom
register block.
Registers are accessed only via the USB interface by the XR_SET_REG and XR_GET_REG commands listed
in Table 4. The register address offsets are given in Table 6, Table 7 and Table 15, and the register blocks
are given in Table 5.
3.1
UART Manager Registers..
3.1.1
FIFO_ENABLE Registers
Enables the RX FIFO and TX FIFOs. For proper functionality, the UART TX and RX must be enabled in the
following order:
FIFO_ENABLE_CHx = 0x1
// Enable TX FIFO
UART_ENABLE = 0x3
// Enable TX and RX of that channel
FIFO_ENABLE_CHx = 0x3
// Enable RX FIFO
3.1.2
RX_FIFO_RESET and TX_FIFO_RESET Registers
Writing a non-zero value to these registers resets the FIFOs.
TABLE 6: UART MANAGER REGISTERS
ADDRESS
REGISTER NAME
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
0X10
FIFO_ENABLE_CHA
0
RX
TX
0X11
FIFO_ENABLE_CHB
0
RX
TX
0X12
FIFO_ENABLE_CHC
0
RX
TX
0x13
FIFO_ENABLE_CHD
0
RX
TX
0X18
RX_FIFO_RESET_CHA
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0X19
RX_FIFO_RESET_CHB
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1A
RX_FIFO_RESET_CHC
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1B
RX_FIFO_RESET_CHD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1C
TX_FIFO_RESET_CHA
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1D
TX_FIFO_RESET_CHB
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1E
TX_FIFO_RESET_CHC
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1F
TX_FIFO_RESET_CHD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
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