XR21V1414
27
REV. 1.3.0
4-CH FULL-SPEED USB UART
GPIO_INT_MASK[5:0]: GPIOx Interrupt Mask
Logic 0 = A change on this input causes the device to generate an interrupt packet.
Logic 1 = A change on this input does not cause the device to generate an interrupt packet.
GPIO_INT_MASK[7:6]: Reserved
These register bits are reserved and should be ’0’.
3.3.15
GPIO_SET Register Description (Read/Write)
Writing a ’1’ in this register drives the GPIO output high. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused
and should be ’0’.
3.3.16
GPIO_CLEAR Register Description (Read/Write)
Writing a ’1’ in this register drives the GPIO output low. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused
and should be ’0’.
3.3.17
GPIO_STATUS Register Description (Read-Only)
This register reports the current state of the GPIO pin.
3.4
UART Custom Registers
TABLE 15: UART CUSTOM REGISTERS
ADDRESS
REGISTER NAME
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
0X03
UART CHAN A CUSTOM
0
MaxPkt-
Size
WIDE_E
N
0X04
UART CHAN A
LOW_LATENCY
0
EN
0X06
UART CHAN A
CUSTOM_INT_PACKET
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1
0X0B
UART CHAN B CUSTOM
0
MaxPktSize
WIDE_EN
0X0C
UART CHAN B
LOW_LATENCY
0
EN
0X0E
UART CHAN B
CUSTOM_INT_PACKET
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1
0X13
UART CHAN C CUSTOM
0
MaxPktSize
WIDE_EN
0X14
UART CHAN C
LOW_LATENCY
0
EN
0X16
UART CHAN C
CUSTOM_INT_PACKET
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1
0X1B
UART CHAN D CUSTOM
0
MaxPktSize
WIDE_EN
0X1C
UART CHAN D
LOW_LATENCY
0
EN
0X1E
UART CHAN D
CUSTOM_INT_PACKET
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1