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參數(shù)資料
| 型號(hào)： | XR21V1414IM48-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 21/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO USB QUAD 48TQFP |
| 產(chǎn)品培訓(xùn)模塊： | UART Product Overview XR21V141x Full-Speed USB UART Family |
| 特色產(chǎn)品： | XR21V141x Full-Speed USB UART |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 1，UART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | USB 2.0 |
| 電源電壓： | 3.3V |
| 帶自動(dòng)流量控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 配用： | 1016-1303-ND - EVAL BOARD FOR XR21V1414IM |
| 其它名稱： | 1016-1304 |
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XR21V1414
28
4-CH FULL-SPEED USB UART
REV. 1.3.0
3.4.1
CUSTOM Register Description (Read/Write)
This register enables the Wide mode functionality for the UART.
CUSTOM[0]: Enable wide mode
Logic 0 = Normal (7, 8 or 9 bit data) mode
Logic 1 = Wide mode - See “Section 1.5.1.1, Wide Mode Transmit” on page 11, “Section 1.5.2.3, Wide
mode receive operation with 7 or 8-bit data” on page 12 and “Section 1.5.2.4, Wide mode receive
operation with 9-bit data” on page 12.
CUSTOM[1]: Max Packet Size
Logic 0 = bMaxPacketSize = 64 bytes
Logic 1 = bMaxPacketSize = 63 bytes (this bit is automatically set to ’1’ if the XR21V1414 receives a
CDC_ACM USB command)
CUSTOM[7:2]: Reserved
These bits are reserved and should remain ’0’.
3.4.2
LOW_LATENCY Register Description (Read/Write)
This register is automatically set to logic ’1’ for baud rates below 46921 bps, and can be manually set for baud
rates of 46921 bps and higher. This register enables the Low latency feature of the UART. Write to this
register following any desired baud rate setting change.
LOW_LATENCY[0]: Enable Low Latency mode
Logic 0 = Receive data is not forwarded from the Rx FIFO until bMaxPacketSize (64 bytes) or timeout (3
characters) has occurred.
Logic 1 = All data in the RX FIFO is provided to the USB host at the next BULK IN request irrespective of the
number of bytes in the FIFO.
LOW_LATENCY[7:1]: Reserved
These bits are reserved and should remain ’0’.
3.4.3
CUSTOM_INT_PACKET (Read/Write)
This register is used to enable / disable GPIO status in the high data byte of the custom interrupt packet. See
Table 16, “Interrupt Packet Format,” on page 29 and Table 18, “Data Field of Customized Interrupt
Packet - Exar Vendor Specific,” on page 30.
CUSTOM_INT_PACKET[0]: GPIO1
Logic 0 = Disable GPIO1 status in custom interrupt packet.
Logic 1 = Enable GPIO1 status in custom interrupt packet.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR21V1414IM48-F | 制造商:Exar Corporation 功能描述:IC QUAD UART 12MBPS 3.63V 48-TQFP |
| XR21V1414IM48TR-F | 制造商:Exar Corporation 功能描述:USB-to-UART 4-CH 128Byte FIFO 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR21V1414 Series 12 Mbps 3.63 V Quad Channel USB UART SMT - TQFP-48 制造商:Exar Corporation 功能描述:XR21V1414IM48TR-F 制造商:EXAR 功能描述:USB-to-UART 4-CH 128Byte FIFO 48-Pin TQFP T/R |
| XR21V1414M48-F | 制造商:Exar Corporation 功能描述:UART 4-CH FULL SPEED USB I/F 48TQFP 制造商:Exar Corporation 功能描述:UART, 4-CH FULL SPEED, USB I/F, 48TQFP, No. of Channels:4, Data Rate:12Mbps, Sup |
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