參數(shù)資料
型號(hào): XRK39653IQ
廠商: EXAR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: 3.3V, 8-OUTPUT ZERO DELAY BUFFER
中文描述: 39635 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, TQFP-32
文件頁(yè)數(shù): 4/9頁(yè)
文件大?。?/td> 76K
代理商: XRK39653IQ
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
xr
REV. 1.0.0
4
a.
VCMR is the cross point of the differential input signal.
.
DC C
HARACTERISTICS
(V
CC
= 3.3 + 5%, T
A
= -40
°
C
TO
+85
°
C)
S
YMBOL
C
HARACTERISTICS
M
IN
T
YP
M
AX
U
NIT
C
ONDITION
V
CMRa
PECL Clock inputs common mode range
1.0
V
DD
-0.6
V
LVPECL
V
PP
PECL Clock peak-to-peak input voltage
300
1000
mV
LVPECL
V
IH
Input voltage high
2.0
V
DD
+0.3
V
LVCMOS
V
IL
Input voltage low
0.8
V
LVCMOS
V
OH
Output High Voltage
a
2.4
V
I
OH
=-24mA
V
OL
Output Low Voltage
a
0.55
0.30
V
V
I
OL
=24mA
I
OL
=12mA
Z
OUT
Output Impedance
14-17
Ω
I
IN
Input leakage current
+200
μΑ
V
IN
=V
DD
or V
IN
=GND
I
CC_PLL
Maximum PLL supply current
5.0
10.0
mA
AV
DD
pin
I
CCQ
Maximum Quiescent supply current
10.0
mA
All V
DD
pins, OE=1
V
TT
Output Termination Voltage
V
CC
÷2
V
AC C
HARACTERISTICS
(V
CC
= 3.3 + 5%, T
A
= -40
°
C
TO
+85
°
C)
a
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NIT
C
ONDITION
f
VCO
VCO Frequency
200
500
MHz
f
ref
Input Reference Frequency ÷4 feedback
÷8 feedback
PLL Bypass
50
25
0
125
62.5
200
MHz
PLL locked
PLL locked
bypass mode
f
MAX
Max Output Frequency ÷4 feedback
÷8 feedback
50
25
125
62.5
MHz
PLL locked
PLL locked
V
PP
PECL Clock peak-to-peak input voltage
450
1000
mV
LVPECL
V
CMR
PECL input Common Mode range
1.2
V
DD
-0.75
V
LVPECL
t
PW Min
Input Reference Clock Minimum Pulse Width
2
ns
t
SPO
Propagation Delay - Static Phase Offset (PECL
to FB_IN)
-75
125
ps
PLL locked
t
PD
Propagation Delay - PLL Bypassed
Bypass mode 1 (BYPASS = 0)
Bypass mode 2, (BYPASS = 1, PLL_EN = 0)
1.2
3.0
3.3
7.0
ns
ns
t
skew(O)
Output-to-Output Skew
150
ps
t
skew(PP)
Part to Part Skew (bypass PLL & divider)
1.5
ns
BYPASS=0
t
JIT(CC)
Cycle-to-Cycle Jitter
100
ps
相關(guān)PDF資料
PDF描述
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