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參數(shù)資料
| 型號： | XRK39910CD-2 |
| 廠商： | EXAR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V LOW SKEW PLL CLOCK DRIVER |
| 中文描述： | 39910 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.300 INCH, SOIC-24 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 80K |
| 代理商： | XRK39910CD-2 |
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XRK39910
3.3V LOW SKEW PLL CLOCK DRIVER
JULY 2006
REV. 1.0.0
FUNCTIONAL DESCRIPTION
The XRK39910 is a high fanout phase locked-loop
clock driver intended for high performance computing
and data-communications applications. It has eight
zero delay LVTTL outputs.
When the OE pin is held low, all the outputs are syn-
chronously enabled. However, if OE is held high, all
the outputs except Q
2
and Q
3
are synchronously dis-
abled.
Furthermore, when the PE is held high, all the outputs
are synchronized with the positive edge of the CLKIN.
When PE is held low, all the outputs are synchronized
with the negative edge of CLKIN.
The FB_IN signal is compared with the input CLKIN
signal at the phase detector in order to drive the
VCO. Phase differences cause the VCO of the PLL to
adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the
VCO to the phase detector. The loop filter transfer
function has been chosen to provide minimal jitter (or
frequency variation) while still providing accurate
responses to input frequency changes.
FEATURES
Eight zero delay outputs
12mA balanced drive outputs
Output frequency: 15MHz to 85MHz
<250ps of output to output skew
Low Jitter: <200ps peak-to-peak
3 skew grades
External feedback, internal loop filter
Selectable
positive
synchronization
Synchronous output enable
3-level inputs for PLL range control
PLL bypass for DC testing
Available in SOIC package
or
negative
edge
F
IGURE
1. F
UNCTIONAL
B
LOCK
D
IAGRAM
PLL
Ref
Feedback
VCO
H
M
L
CLKIN
FB_IN
FSEL*
PE
Bypass*
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
* Tri-Level inputs
F
IGURE
2. P
IN
C
ONFIGURATION
CLKIN
V
DDPLL
FSEL
nc
PE
V
DD
Q0
Q3
Q1
GND
Q2
GND
Bypass
nc
OE
Q7
Q6
GND
Q5
Q4
FB_IN
V
DD
V
DD
V
DD
XRK39910
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRK39910CD-5 | 3.3V LOW SKEW PLL CLOCK DRIVER |
| XRK39910ID-2 | 3.3V LOW SKEW PLL CLOCK DRIVER |
| XRK49911 | 3.3V HIGH-SPEED (110 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER |
| XRK49911CJ-2 | 3.3V HIGH-SPEED (110 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER |
| XRK49911IJ-2 | 3.3V HIGH-SPEED (110 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRK39910CD-5 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V LOW SKEW PLL CLOCK DRIVER |
| XRK39910CD-7 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V LOW SKEW PLL CLOCK DRIVER |
| XRK39910ID-2 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V LOW SKEW PLL CLOCK DRIVER |
| XRK39910ID-5 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V LOW SKEW PLL CLOCK DRIVER |
| XRK39910ID-7 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V LOW SKEW PLL CLOCK DRIVER |
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