• 參數(shù)資料
    型號: XRK39910CD-2
    廠商: EXAR CORP
    元件分類: 時鐘及定時
    英文描述: 3.3V LOW SKEW PLL CLOCK DRIVER
    中文描述: 39910 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
    封裝: 0.300 INCH, SOIC-24
    文件頁數(shù): 3/9頁
    文件大?。?/td> 80K
    代理商: XRK39910CD-2
    XRK39910
    3
    REV. 1.0.0
    3.3V LOW SKEW PLL CLOCK DRIVER
    N
    OTE
    :
    1.
    2.
    3.
    Tri-Level Input
    When BYPASS = MID and OE = HIGH, PLL remains active.
    This input is wired to V
    DD
    , GND, or unconnected. Default is MID level. If it is switched in the real time mode, the
    outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved.
    Q
    0
    - Q
    7
    7,8,10,11,
    15,16,18,19
    OUT
    Eight clock output.
    GND
    9,17,24
    PWR
    Ground.
    FB_IN
    13
    IN
    Feedback Input
    OE
    (2)
    21
    IN
    Synchronous Output Enable. When HIGH, it stops clock outputs (except Q
    2
    and
    Q
    3
    ) in a LOW state - Q
    2
    and Q
    3
    may be used as the feedback signal to maintain
    phase lock. Set OE
    LOW for normal operation.
    BYPASS
    (1,2)
    23
    IN
    When MID or HIGH, disable PLL (except for conditions of Note 2). CLKIN goes to
    all outputs. Set LOW for normal operations.
    T
    ABLE
    5: R
    ECOMMENDED
    O
    PERATING
    R
    ANGE
    SYMBOL
    D
    ESCRIPTION
    XRK39910-2, -5, -7
    (I
    NDUSTRIAL
    )
    XRK39910-2, -5, -7
    (C
    OMMERCIAL
    )
    U
    NIT
    M
    IN
    .
    M
    AX
    .
    M
    IN
    .
    M
    AX
    .
    V
    DD
    Power Supply Voltage
    3
    3.6
    3
    3.6
    V
    T
    A
    Ambient Operating Temperature
    -40
    +85
    0
    +70
    °C
    T
    ABLE
    6: DC E
    LECTRICAL
    C
    HARACTERISTICS
    OVER
    O
    PERATING
    R
    ANGE
    S
    YMBOL
    P
    ARAMETER
    C
    ONDITIONS
    M
    IN
    .
    M
    AX
    .
    U
    NIT
    V
    IH
    Input HIGH Voltage
    Guranteed Logic HIGH
    (CLKIN, FB_IN, OE, PE Inputs
    Only)
    2
    V
    V
    IL
    Input LOW Voltage
    Guaranteed Logic LOW
    (CLKIN, FB_IN, OE, PE Inputs
    Only)
    0.8
    V
    V
    IHH
    Input HIGH Voltage
    (1)
    3-Level Inputs Only
    (FSEL, BYPASS)
    V
    DD
    -0.6
    V
    V
    IMM
    Input MID Voltage
    (1)
    3-Level Inputs Only
    (FSEL, BYPASS)
    V
    DD
    /2-0.3
    V
    DD
    /2+0.3
    V
    V
    ILL
    Input LOW Voltage
    (1)
    3-Level Inputs Only
    (FSEL, BYPASS)
    0.6
    V
    I
    IN
    Input Leakage Current
    (CLKIN, FB_IN Inputs Only)
    V
    IN
    = V
    DD
    or GND
    V
    DD
    = Max.
    +5
    μ
    A
    T
    ABLE
    4: P
    IN
    D
    ESCRIPTIONS
    P
    IN
    N
    AME
    P
    IN
    N
    UMBER
    T
    YPE
    D
    ESCRIPTION
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