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參數(shù)資料
| 型號(hào)： | XRK4991IJ-5 |
| 廠商： | EXAR CORP |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER |
| 中文描述： | 4991 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | GREEN, PLASTIC, LCC-32 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 98K |
| 代理商： | XRK4991IJ-5 |
xr
REV. 1.0.1
XRK4991
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
3
PIN DESCRIPTIONS
P
IN
N
AME
P
IN
#
T
YPE
D
ESCRIPTION
CLKIN
1
I
Reference clock input.
FB_IN
17
I
PLL’s feedback input. (Normally connected to one of the eight outputs)
FSEL
3
I
Tri-level frequency range select. See Table 1
PLL_BYPASS
31
I
Tri-level select. See PLL_BYPASS section.
SELA0
SELA1
26
27
I
Tri-level select inputs for Bank A outputs (QA0, QA1). See Table 2.
SELB0
SELB1
29
30
I
Tri-level select inputs for Bank B outputs (QB0, QB1). See Table 2.
SELC0
SELC1
4
5
I
Tri-level select inputs for Bank C outputs (QC0, QC1). See Table 2.
SELD0
SELD1
6
7
I
Tri-level select inputs for Bank D outputs (QD0, QD1). See Table 2.
QA0
QA1
24
23
O
Bank A output pair. See Table 2.
QB0
QB1
20
19
O
Bank B output pair. See Table 2.
QC0
QC1
15
14
O
Bank C output pair. See Table 2.
QD0
QD1
11
10
O
Bank D output pair. See Table 2.
V
CCN
9
16
18
25
PWR
Power supply for output drivers.
V
CCQ
2
8
PWR
Power supply for internal circuitry.
GND
12
13
21
22
28
32
PWR
Ground.
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| XRK4993 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:3.3V PROGRAMMABLE SKEW CLOCK BUFFER |
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| XRK4993CR-5 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:3.3V PROGRAMMABLE SKEW CLOCK BUFFER |
| XRK4993CR-7 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:3.3V PROGRAMMABLE SKEW CLOCK BUFFER |
| XRK4993IR-2 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:3.3V PROGRAMMABLE SKEW CLOCK BUFFER |
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