參數(shù)資料
型號(hào): XRK4991IJ-5
廠商: EXAR CORP
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
中文描述: 4991 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32
封裝: GREEN, PLASTIC, LCC-32
文件頁(yè)數(shù): 5/12頁(yè)
文件大?。?/td> 98K
代理商: XRK4991IJ-5
xr
REV. 1.0.1
XRK4991
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
5
PLL_BYPASS
The PLL_BYPASS input is a tri-level input. In normal system operation, this pin is connected to ground.
In normal operation (tied LOW) all outputs will function based only on the connection of their own function
select inputs (SELx[1:0]) and the waveform characteristics of the PLL.
If the PLL_BYPASS input is forced to its MID or HIGH state the device will operate in PLL bypass mode, with
the phase locked loop disconnected, and CLKIN waveforms will directly control all outputs. Relative output to
output timing is controlled by the SELx[1:0], the same as in normal mode.
F
IGURE
3. T
YPICAL
O
UTPUTS
WITH
FB_IN C
ONNECTED
TO
A
Z
ERO
-S
KEW
O
UTPUT
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
(N/A)
HH(D)
-6t
U
-4t
U
-3t
U
-2t
U
-1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
DIVIDED
INVERT
SELA[1:0]
SELB[1:0]
SELC[1:0]
SELD[1:0]
FB_IN
CLKIN
t
0
-
U
t
0
-
U
t
0
-
U
t
0
-
U
t
0
-
U
t
0
-
U
t
0
t
0
+
U
t
0
+
U
t
0
+
U
t
0
+
U
t
0
+
U
t
0
+
U
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