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參數(shù)資料
| 型號： | XRK4993IR-2 |
| 廠商： | EXAR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V PROGRAMMABLE SKEW CLOCK BUFFER |
| 中文描述： | 4993 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.150 INCH, QSOP-28 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 95K |
| 代理商： | XRK4993IR-2 |
XRK4993
5
REV. 1.0.0
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
In the PLL_BYPASS mode the PE input can be used to invert the outputs. Thus, for a 20% (High) duty cycle
input, all outputs will retain the 20% high condition with PE High. For PE Low, however, they will be 80% High.
PE does not effect the duty cycle of the divided outputs.
SPECIAL FUNCTIONS
The following special functions have been implemented in the chip.
PE pin:
In Normal operation, PE controls the "alignment" edge of the CLKIN and the FB-IN signals. (All other output signals are
aligned to the Feedback). PE=Low, aligns the FB_IN faliing edge to the CLKIN falling edge. PE=High, aligns rising
edges.
In the "disabled output mode (see below), the disabled state is forced to the opposite state of PE. This keeps the off
condition in a low-noise state.
In PLL_BYPASS mode, PE controls the duty cycle (inversion) of the outputs (see PLL_BYPASS mode above).
OE pin:
In Normal mode, OE is used to disable all outputs except QC[1,0]. These are maintained to provide PLL Feedback to
keep frequency lock. OE is kept low to enable the outputs and High to disable them. This is a synchronized operation to
prevent "partial" clocks When OE goes high, the outputs will go to their disabled level at the end of the next active clock
cycle. The level is determined by the state of PE. If PE is high, the output will go low at the end of the cycle and remain
there until OE return to a low state. If PE is low, at the end of the next clock high state it will continue to remain high until
OE returns low.
If OE is high when PLL_BYPASS is at the Mid level, the PLL is enabled to provide an individual bank output control. In
this mode, taking both SEL(x)1 & 0 to the Low state will disable that bank's outputs.
T
ABLE
3: T
YPICAL
PROPAGATION
DELAY
WITH
ZERO
SKEW
SETTING
PLL_BYPASS I
NPUT
FSEL I
NPUT
T
OTAL
PROPAGATION
DELAY
Mid
Low or Mid
52nS
High
29nS
High
Low or Mid
12nS
High
10nS
F
IGURE
3. T
YPICAL
O
UTPUTS
WITH
FB_IN C
ONNECTED
TO
A
Z
ERO
-S
KEW
O
UTPUT
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
-6t
U
-4t
U
-3t
U
-2t
U
-1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
DIVIDED
SELA1:0]
SELB1:0]
SELC1:0]
FB_IN
CLKIN
t
0
-
U
t
0
-
U
t
0
-
U
t
0
-
U
t
0
-
U
t
0
-
U
t
0
t
0
+
U
t
0
+
U
t
0
+
U
t
0
+
U
t
0
+
U
t
0
+
U
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRK4993IR-5 | 3.3V PROGRAMMABLE SKEW CLOCK BUFFER |
| XRK69772 | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69772CR | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69772IR | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69773 | 1:12 LVCMOS PLL CLOCK GENERATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRK4993IR-5 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PROGRAMMABLE SKEW CLOCK BUFFER |
| XRK4993IR-7 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PROGRAMMABLE SKEW CLOCK BUFFER |
| XRK69772 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69772CR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69772IR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
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