參數(shù)資料
型號(hào): XRK4993IR-5
廠商: EXAR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: 3.3V PROGRAMMABLE SKEW CLOCK BUFFER
中文描述: 4993 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝: 0.150 INCH, QSOP-28
文件頁數(shù): 3/13頁
文件大?。?/td> 95K
代理商: XRK4993IR-5
XRK4993
3
REV. 1.0.0
PIN DESCRIPTIONS
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
P
IN
N
AME
P
IN
#
T
YPE
D
ESCRIPTION
CLKIN
1
Input
Reference Clock Input
FB_IN
14
Input
Feedback Input
PLL_BYPASS
27
Three-
level
Input
When MID or HIGH, disables PLL (see Special Functions). CLKIN goes to all out-
puts. Skew Selections (see Control Summary Table) remain in effect. Set LOW
for normal operations.
OE
24
Input
Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0]).
QC[1:0]
may be used as the feedback signal to maintain phase lock. Set OE
LOW for normal operation.
PE
6
Input
Selectable positive or negative edge control. When LOW/HIGH the outputs are
synchronized with the falling/rising edge of the reference clock.
SELA0
SELA1
22
23
Three-
level
Input
3-level inputs for selecting 1 of 9 skew taps or frequency functions.
SELB0
SELB1
25
26
Three-
level
Input
SELC0
SELC1
4
5
Three-
level
Input
FSEL
3
Three-
level
Input
Selects appropriate oscillator circuit based on anticipated frequency range. (See
PLL Programmable Skew Range.)
QA0
QA1
20
19
Output
Three output banks of two outputs with programmable skew (QA[1:0], QB[1:0],
QC[1:0]). QD[1:0] outputs have fixed zero skew outputs.
QB0
QB1
16
15
Output
QC0
QC1
12
11
Output
QD0
QD1
9
8
Output
V
CCN
7
13
21
PWR
Power supply for output buffers.
V
CCQ
2
PWR
Power supply for phase locked loop and other internal circuitry.
GND
10
17
18
28
PWR
Ground.
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