參數(shù)資料
型號: XRK69772CR
廠商: EXAR CORP
元件分類: XO, clock
英文描述: 1:12 LVCMOS PLL CLOCK GENERATOR
中文描述: 240 MHz, OTHER CLOCK GENERATOR, PQFP52
封裝: 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52
文件頁數(shù): 5/12頁
文件大小: 97K
代理商: XRK69772CR
PRELIMINARY
XRK69772
5
REV. P1.0.0
1:12 LVCMOS PLL CLOCK GENERATOR
T
ABLE
4: AC C
HARACTERISTICS
(V
DD
= 3.3V +/- 5%)
S
YMBOL
C
HARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
f
REF
Input reference frequency
a
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
PLL bypass mode
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
6.25
5.00
120
80.0
60.0
48.0
40.0
30.0
24.0
20.0
15.0
12.0
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
f
VCO
VCO frequency range
200
480
MHz
f
XTAL
Crystal input frequency range
10
25
MHz
f
MAX
Output frequency
a
÷2 output
÷4 output
÷6 output
÷8 output
÷10 output
÷12 output
÷16 output
÷20 output
÷24 output
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
240.0
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
f
STOP_CLK
Serial interface max.
frequency
20.0
MHz
t
PW
CLKx pulse min. width
2.0
ns
It
R
, It
F
Input CLKx Rise/Fall time
0.8V to 2.0V
1.0
ns
t
(
)
Propagation Delay (static
phase offset) CLKx to FB_IN
b
6.25MHz < f
REF
< 65.0MHz
65.0MHz < f
REF
< 125MHz
f
REF
= 50MHz & FB = ÷8
-3
-4
-166
+3
+4
+166
°
°
ps
t
SK(O)
Output to output skew
c
Bank A (QAx to QAy)
Bank B (QBx to QBy)
Bank C (QCx to QCy)
all outputs (QXy to QWz)
100
100
100
250
ps
ps
ps
ps
DC
Output duty cycle
d
(T÷2)-200
T÷2
(T÷2)+200
ps
Ot
R
, Ot
F
Output Rise/Fall time
0.55V to 2.4V
0.1
1.0
ns
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