參數(shù)資料
型號: XRK69772CR
廠商: EXAR CORP
元件分類: XO, clock
英文描述: 1:12 LVCMOS PLL CLOCK GENERATOR
中文描述: 240 MHz, OTHER CLOCK GENERATOR, PQFP52
封裝: 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52
文件頁數(shù): 6/12頁
文件大?。?/td> 97K
代理商: XRK69772CR
XRK69772
PRELIMINARY
6
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
N
OTES
:
a.
PLL locked, except when configured in bypass mode.
b.
t
()
[s] = t
()
[
°
] ÷ (fref x 360
°)
c.
Not including Qsync output
d.
T is the output period.
T
ABLE
5: AC C
HARACTERISTICS
(
CON
T
) (V
DD
= 3.3V +/- 5%)
S
YMBOL
C
HARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
t
PLZ,
t
PHZ
Output Disable Time
8
ns
t
PZL,
t
PZH
Output Enable Time
8
ns
t
JIT(CC)
Cycle-to-Cycle Jitter
All outputs in same divider
configuration
150
200
ps
t
JIT(PER)
Period Jitter
All outputs in same divider
configuration
150
ps
t
JIT(I/O)RMS
I/O Jitter (RMS)
VCO @ 400MHz
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
11
86
13
88
16
19
21
22
27
30
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
BW
PLL closed loop bandwidth
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
1.20-3.5
0.70-2.50
0.50-1.80
0.45-1.20
0.30-1.00
0.25-0.70
0.20-0.55
0.17-0.40
0.12-0.30
0.11-0.28
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
t
LOCK
Max PLL Lock Time
10
ns
F
IGURE
3. T
EST
L
OAD
V
TT
Z = 50
Ω
Transmission Line
50
Ω
相關(guān)PDF資料
PDF描述
XRK69772IR 1:12 LVCMOS PLL CLOCK GENERATOR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRK69772IR 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR
XRK69773 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR
XRK69773CR 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR
XRK69773IR 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR
XRK69774 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR